1. Field of the Invention
The present invention relates to a circuit verification method for verifying operation of a circuit, a circuit verification apparatus using the circuit verification method, and a circuit verification program for implementing the circuit verification method on the circuit verification apparatus.
2. Description of Related Art
As information technology equipment become sophisticated in functionality, the integration scales of integrated circuits contained in a single semiconductor device are increasing. Designs of highly-integrated system LSI (Large Scale Integration) and SoC (System On a Chip) semiconductor integrated circuits are often described in a HDL (Hardware Description Language). Because designers do not need to know all specifics of a circuit design in HDL, some circuit blocks are treated as the so-called “black box”.
In actual operation of black-box circuit blocks, it is good enough to know which output signal can be obtained in response to which input signal. However, it is necessary to perform simulation at the designing stage to see whether the entire integrated circuit including black-box circuit blocks can achieve a desired operation. In the simulation, data concerning the design of the entire integrated circuit and a library that defines logic information concerning circuit blocks constituting the integrated circuit are used. However, logic information concerning black-box circuit blocks cannot be defined in a library because the logic information is unavailable.
FIG. 1 is a flowchart illustrating a circuit verification method according to a related art. The flowchart includes the step S101 of inputting a design and a library, step S102 of setting a fixed logic value, step S103 of propagating the fixed logic value to the subsequent stage, step S104 of executing fixed value propagation using logic information in a library cell, step S105 of determining whether or not fixed value propagation in the circuit has been completed, and the S106 of executing verification using the results of the fixed value propagation.
In the flowchart of FIG. 1, step S101 is first executed. After step S101, step S102 is executed. After step S102, step S103 is executed. After step S103, step S104 is executed. After step S104, step S105 is executed. If the result of determination at step S105 is “No”, then steps S103 through S105 are executed again. If the result of determination at step S105 is “Yes”, then step S106 is executed. Upon completion of step S106, the process of the flowchart of FIG. 1 will end.
The steps of the flowchart of FIG. 1 will be described in detail.
At step S101, design data concerning a design of a circuit to be verified and a library relating to operation are input.
At step S102, a fixed logic value is set as the initial value for the start point in the circuit to be verified. The start point in the circuit to be verified is a given node in the circuit to be verified, which may be an external input terminal, for example, of the entire circuit to be verified.
At step S103, the design data is traced from the set start point to select the next-stage circuit block to which the fixed logic value is to be propagated.
At step S104, the fixed logic value of the input signal is propagated to an output signal in the selected circuit block on the basis of logic information defined in the library. After the fixed logic value has been propagated, a new circuit block to which the output signal of the selected circuit block is to be input, that is, a subsequent-stage circuit block, is selected.
At step S105, determination is made as to whether or not possible fixed logic value propagation has been performed in all circuit blocks of the entire circuit to be verified.
At step S106, the propagated fixed logic value is used to perform various kinds of verifications on the circuit to be verified.
Relating to the foregoing, Patent Document (Japanese Patent Application Laid-Open No. 2007-140877) discloses a logical equivalence verification system. The logical equivalence verification system described in Patent Document includes an RTL (Register Transfer Level)/gate level circuit description, a library, and a logical equivalence verification unit. The RTL/gate level circuit description includes RTL circuit description information and gate level description information. The library includes information for executing logical equivalence verification. The logical equivalence verification unit includes a compiler, a verification circuit database, a logical equivalence verification processing unit, and black-box cell transforming means. The compiler generates a circuit database from the RTL/gate level circuit description information and the library information. The circuit verification database generates a reference circuit database for generating reference circuit information from information output from the compiler and verification circuit information from information output from the compiler. The logical equivalence verification processing unit executes verification processing based on information output from the reference circuit database and the verification circuit database. The black box cell transforming means provides a given logic to a black box cell to transform the black box cell to a function cell.